Generally, transistors in a bipolar type semiconductor integrated circuit device are produced in electrically independent islands that are separated from adjacent transistors by a pn junction separation method, a oxide film separation method using an selective oxidation technique, or a diffusion method. Herein, a method of producing an npn transistor by an oxide film separation method will be described. Of course, various separation methods other than this oxide film separation method may be used, and transistors may be of pnp types.
FIGS. 10(A) to (E) show the cross-sectional structures of a prior art semiconductor integrated circuit device at major process steps in a prior art production method. The prior art production method will be briefly described in the following.
At first, a high impurity density n type (n.sup.+ type) layer 2 which becomes a collector embedded layer is selectively produced on a low impurity density p type (p.sup.- type) silicon substrate 1. Next, an n.sup.- type epitaxial layer 3 will be produced on the silicon substrate 1 on and the n.sup.+ type layer 2 (FIG. 10(A)).
Thereafter, an underlying oxide film 101 and a nitride film 201 are produced on a predetermined region of the n.sup.- layer 3, and a channel cutting p type layer 4 is annealed by using the nitride film 201 as a mask. At the same time, a thick separation oxide film 102 is produced by using the nitride film 201 as a mask (FIG. 10(B)).
Next, the nitride film 201 which has been used as a mask for the selective oxidation is removed together with the underlying oxide film 101. Thereafter, an oxide film 103, which is used for protection from ion injection, is produced, and a p.sup.+ type layer 5, which becomes an external base layer, is produced by using the photoresist film (the photoresist film at this step is not shown) as a mask. Furthermore, the above-described photoresist film is removed, and a photoresist film 301 is produced in a predetermined configuration. A p type layer 6, which becomes an active base layer is produced by an ion injection method by using the photoresist film 301 as a mask (FIG. 10(C)).
Subsequently, the photoresist film 301 is removed, and a passivation film 401 which generally comprises phosphorus silicate glass coats the surface. A thermal process which functions to anneal the base ion injection layers 5 and 6 and the sintering of the PSG film 401, is conducted, and an intermediate stage external base layer 51 and an intermediate stage active base layer 61 are produced. Next, an emitter electrode contact hole 70 and a collector electrode contact hole 80 are produced at predetermined regions of the PSG film 401. An n.sup.+ type layer 7, which becomes an emitter layer, and an n.sup.+ type layer 8, which becomes a leading out collector electrode layer, are produced by ion injection methods through the contact holes 70 and 80 (FIG. 10(D)).
Thereafter, the respective ion injection layers are annealed, the external base layer 52 and the active base layer 62 are completed, and the emitter layer 71 and the leading out collector electrode layer 81 are produced. Furthermore, a metal silicide film 501 for preventing electrode extrusion (such as for preventing the reaction between aluminum and silicon) is produced at each of the respective holes 50, 70 and 80 produced on the PSG film 401. For this metal silicide film 501, platinum silicide (Pt-Si) or palladium silicide (Pd-Si) may be used. Thereafter, a base electrode wiring 9, an emitter electrode wiring 10, and a collector electrode wiring 11 are produced with the use of a low resistance metal, such as aluminum, on the metal silicide film 501 (FIG. 10(E)).
Also, the frequency characteristics of a transistor depend on the base-collector capacitance and the base resistance. Thus, it is necessary to lower these in order to enhance the frequency characteristics of a transistor. The p.sup.+ external base layer 52 in the above-described prior art structure is provided so as to lower the base resistance. However, the external base layer 52 is produced with position the overlap in the photolithography process that does not self-align with the emitter layer 71. Therefore, the external base layer has to be produced to some extent apart therefrom, result in the remaining high resistance base layer 62 in a wide region. The result is that the base resistance is not lowered as much as expected.
Furthermore, the base resistance depends on the distance D1 between the emitter layer 71 and the leading out base electrode aperture 50 as shown in the plain pattern of the transistor that is produced by the prior art method of FIG. 11. In the prior art device, the distance D1 is the sum of the interval between the base electrode wiring 9 and the emitter electrode wiring 10 and the lengths of the portions of the electrode wirings 9 and 10 extending out from the respective apertures 50 and 70. Thus, even if the preciseness of the photo etching is enhanced to narrow the electrode wiring interval, the above-described extending out portions inevitably remain, and the base resistance can not be lowered as much.
Furthermore, although such a double base structure as shown in FIG. 6 is frequently used as a method for reducing the base resistance, there are disadvantages because the base region increases due to the leading out of the base electrode, for example, which results in an increase in the base collector capacitance.
Furthermore, in the prior art method, the plain pattern of the emitter diffusion layer 71 is dependent on the photolithography preciseness. Although the photolithography preciseness of about 1 micron is put into practice by the highest present level photolithography technique, a high performance photolithography device is required and a further fine pattern is quite difficult to produce. Herein, the reduction of the width of the emitter diffusion layer (emitter width) reduces the emitter area as well as reducing the capacitance of an emitter base junction. Further, a base resistance is reduced (R. M. Warner and J. N. Fordemwolt, "Integrated Circuits," pp. 103-109, McGraw-Hill, New York, 1985). Accordingly, although fine patterning of the emitter width is required in order to improve the frequency characteristics, a problem in the fine patterning of the emitter width being restricted by the photolithography preciseness occurs in the prior art method.
FIG. 13(A) to FIG. 13(I) show cross-sectional views at the major production process steps of another prior art method for producing a semiconductor integrated circuit device. This second prior art production method will be described in the following.
FIG. 13(A)
At first, a high impurity density n type (n.sup.+ type) layer 2, which becomes a collector embedded layer, is selectively produced on a low impurity density p type p.sup.- type) silicon substrate 1. Thereafter, a low impurity density n type (n.sup.- type) epitaxial layer 3 is grown thereon.
FIG. 13(B)
An underlying oxide film 1101 is produced on the epitaxial layer 3, and a nitride film 1201 having a predetermined configuration is produced on the underlying oxide film 1101. A thick separation oxide film 1102 is produced by conducting a selective oxidation which uses the nitride film 1201 as a mask. At the same time, a channel cutting p type layer 4 is produced below the separation oxide film 1102.
FIG. 13(C)
After removing the nitride film 1201, which has been used as a selective oxidation mask, together with the underlying oxide film 1101, an oxide film 1103 for ion injection protection is produced. A p type layer 6 which becomes an active base layer is produced by conducting an ion injection which uses a photoresist film that is produced on the oxide film 1103 as a mask (the photoresist film at this step is not shown). Thereafter, an oxide film 1103 in the neighborhood of the region which will become a base electrode aperture is removed. Next, a silicon film 1601 is coated over the exposed entire surface. Herein, film a mono-crystalline silicon a poly-crystalline silicon film, or an amorphous silicon film may be used as the silicon film.
FIG. 13(D)
An intermediate stage active base region 61 is produced at the p type layer 6 by sintering after introducing p type impurities into the entire surface of the silicon film 1601. At the same time, an external base region 51 is produced by conducting an impurity diffusion by p type impurities the silicon film 1601. Thereafter, the silicon film 1601 is selectively etched and removed, and a silicon film remains on the external base region 51 and the separation oxide film 1102. An oxide film 1105 is produced on the position where the oxided film 1103 has been produced, and an oxide film 1106 is produced over the remaining silicon film 1601 by conducting another oxidation. Further, a phosphorus silicate glass film 1401 is produced on the entire surface.
FIG. 13(E)
By conducting a selective etching that use a photoresist film (not shown) as a mask, apertures are produced by removing the oxide film 1105 and PSG film 1401 on the regions to be used as an emitter layer and a leading out collector electrode layer. Next, a silicon film 1602 is coated over the entire surface, an n type impurities are ion injected into the silicon film 1602 to a high concentration. Next, driving of injected impurities are driven into the silicon film 1602 and diffusion of the impurities into the substrate surface from the silicon film 1602 occurs. Thereby, an n.sup.+ type layer 71, which becomes an emitter layer, and an n.sup.+ type layer 81 which becomes a leading out a collector electrode layer are produced. Then, impurities are also driven to the external base region 51 and an external base region 52 is produced.
FIG. 13(F)
A selective etching of the silicon film 1602 is conducted so that the silicon film portion 1602a and 1603 remain which have become impurity diffusion sources. Next, aperturing of a contact hole for a base contact is conducted from the resist film 1302 which is patterned in a predetermined configuration as a mask. Then, the resist film 1302 exposes a portion of the silicon film 1602a for producing the emitter layer, and the base contact, the oxide film 1106 and the PSG film 1401 on the silicon film 1601 following the base contact are etched and removed with the exposed silicon film 1602a acting as a mask.
FIG. 13(G)
An oxidation at a low temperature (about 800.degree. C. to 900.degree. C.) produces a thick oxide film 1108 on the polysilicon films 1602a and 1603 and on the n.sup.+ layers 71 and 81. Also, a thin oxide 1107 is produced on the p type region 62 and the p.sup.+ type silicon film 1601. This is produced with the use of the well known fact that the lower the temperature is the more the acceleration is conducted in the silicon substrate and the silicon film including phosphor and arsenic at n type impurities at a high concentration.
FIG. 13(H)
Only the thin oxide film 1107 is washed out. Next, a metal layer (not shown) is produced by the use of a vapor plating method or a sputtering method on the entire surface from the use of metals, such as Pt, Pd, Ti, W, and Mo, which produce a metal silicide with silicon or polysilicon film. Thereafter, a sintering process is conducted to produce metal silicide films 1501 and 1502 on the exposed surface of the silicon substrate and the silicon film 1601. Thereafter, the metal layer is removed by an etching, such as aqua regia, so as to the metal silicide film remains.
FIG. 13(I)
After a passivation nitride film 1202 (an oxide film may be used) is coated over the surface, a selective etching is executed the nitride film 1202 and the thick oxide film 1108 so that, and the base electrode contact hole 50, emitter electrode contact hole 70, and collector electrode contact hole 80 are apertured. Next, a base electrode wiring 9, emitter electrode wiring 10, and collector electrode wiring 11 are respectively produced by using a low resistance metal such as aluminum.
FIG. 14 shows a plain pattern of a transistor produced through the production process shown in FIG. 13(A) to FIG. 13(I). In FIG. 14, the distance C designates a distance between the emitter layer 71 and the polysilicon film 1601 that is connected to the base electrode 9, and the distance D designates a distance between the emitter layer 71 and the separation oxide film 1102. The aperture photolithography for producing the emitter layer 71 (production of the aperture portion) is conducted by aligning either of the patterns of the separation oxide film 1102 or the polysilicon film 1601. The interval between either of the films and the emitter layer 71 must be made larger than the overlapping margin of the photolithography (an overlapping margin corresponding to twice photolithography is required). Because the aperture photolithography for producing the emitter layer 71 is generally conducted by aligning with the pattern of the separation oxide film 1102, it is necessary to increase the distance C (to a value larger than about twice of the overlapping margin). This increase in the distance C causes an increase in the base area and increases in base collector capacitance results.
FIG. 15 shows cross-sections illustrating the variation in the distance between the emitter layer and the polysilicon film that is connected to the base electrode and is caused by the overlapping preciseness of the photolithography. The dependency of the distance C on the photolithography overlapping preciseness will be described with in the following.
As shown in FIG. 15(A), the polysilicon film 1601, which usually becomes a base electrode, is photolithographically aligned with the separation edge (the end portion of the separation oxide film 1102) as shown in the drawing by an arrow A, the emitter contact is also photolithographically aligned with the separation edge (arrow B), and the silicon film 1602a, which becomes an emitter electrode, is photolithographically aligned with the contact pattern. Accordingly, the distance between the silicon films (corresponding to the distance C of FIG. 14) is determined by the overlapping preciseness of the photolithography. In the worse case, the inter-silicon film distance C greatly varies in a range from below half to three times of that in the normal case as shown in FIGS. 15(B) and (C).
FIG. 16 shows a plain pattern a transistor of which adopts a double base structure having the above-described distances C at both sides of the emitter so as to suppress the variation of the above-described distance C.
In this double base structure an active base region 62 is produced by surrounding the emitter layer 71. The silicon films 1601 on the external base region are produced so that they are put between the emitter layer and are connected to the base electrode wiring 11 through bode side contact holes 50.
FIG. 17 shows a cross-sectional structure of a transistor element having a double base structure that is obtained by the photolithography in the production of the emitter layer where the worst photolithography is conducted. Even when the photolithography overlapping in the production of the emitter layer becomes worst case as shown in FIG. 17 by adopting the double base structure as shown in FIG. 16, the distance E between the silicon film 1601 that is connected to the base electrode and the emitter diffusion layer 71, is required to be set equal to the design value. When such a double base structure is adopted, the inter-silicon film interval C (the distance between the emitter layer and the silicon film that is connected to the base electrode) becomes one including the photolithography overlapping margin, and the incremental portion of the extra base area about doubles by adopting such a double base structure. This becomes a heavy obstruction in the enhancement of the frequency characteristics of the transistor element.